IGFET inverter circuits employing a pair of complementary IGFET devices (CMOS) have been widely employed in the prior art, as is shown in FIG. 1. The CMOS inverter 2 shown in FIG. 1 includes an N channel enhancement mode transistor 4' connected at 164 to the least positive voltage supply 3 and a P channel enhancement transistor 6' connected at 14' to the most positive voltage supply 7, with the common drains 17' and 13' being the output 5. The gate 8' of the P channel device 6' and the gate 10' of the N channel device 4' are connected together and receive the input signal at the terminal 12. When the input signal at 12 is down, the N channel enhancement mode device 4' is turned off and the P channel enhancement mode device 6' is turned on so that the output at 5 is at the level of the most positive supply voltage 7. When the input signal at the input 12 is high, the N channel device 4' is on and the P channel device 6' is off, resulting in the output 5 being at the level of the least positive supply voltage 3. Since one of the devices 4' or 6' of the pair in the circuit 2 is always off during their steady state, this type of circuit dissipates power only during its switching transients. The principal technique for forming CMOS circuits in the prior art is to select a particular conductivity type substrate, for example an N-type substrate and then form first channel type devices, in this example P channel type devices by directly depositing P-type doped regions as the source and drain of the P channel devices into the N-type substrate. Then to form the other channel type or N channel devices, a relatively large island structure had to be formed in the substrate, in this example, for N channel devices in an N-type substrate, a P-type island would have to be formed and then the N-type conductivity source and drain regions be subsequently formed in the P-type island region. Only in this manner could both channel types of FET devices be formed in the same conductivity type semiconductor substrate. Although CMOS circuits having useful properties could be formed with this technique, there were significant accompanying disadvantages, namely that the island region formed in the semiconductor substrate took up a substantially larger area than did the actual FET device formed within it and secondly that the island structure would form parasitic bipolar transistors with other adjacent structures in the semiconductor substrate, producing unwanted electrical characteristics in the overall circuit. The paired wiring of gates for the N channel and P channel devices in conventional CMOS technology consumes considerable silicon real estate.
A suggestion for a solution to this problem was made by K. E. Kroell in his article "Integrated CMOS Structure," in the IBM Technical Disclosure Bulletin, Volume 15, No. 9, Feb. 1973, pages 2856-2857, wherein he describes a shared gate, stacked CMOS structure wherein a pair of oppositely conductive FETs are superimposed upon each other so that the semiconductor space is required for only one MOSFET device. Kroell describes an N channel FET device being formed in a P-type silicon substrate by diffusing N-type source and drain regions directly into the substrate. After covering the channel region with a gate oxide insulator, Kroell deposits a metallization layer of temperature resistant metal and etches a conductor pattern for the common gate electrode and the remaining source and drain contacts for both the N channel device already formed in the substrate and the P channel device to be formed on top of the N channel device. Kroell then deposits a second gate insulating layer on top of the conductive metal gate already deposited on the channel of the N channel device, and then deposits a silicon layer of N-type conductivity on top of the assembly. Kroell then forms the P-type source and drain regions in the upper, N-type silicon layer by either diffusion or ion implantation processes, thereby forming a P channel device which is stacked on top of the N channel device and shares a common gate electrode.
The stacked CMOS structure disclosed by Kroell has a number of practical limitations in its operating characteristics, its amenability to large scale integrated circuit layouts, and its method of fabrication. For example, the N channel device described by Kroell is not self-aligned with respect to its gate. Furthermore, some refractory metals described by Kroell in his structure, such as molybdenum, have serious corrosion problems. With respect to Kroell's P channel device, it too is not self-aligned with its gate. Furthermore, photolithographic tolerances will limit the minimum size of the device since there are two alignment steps which are required in determining the channel length of the P channel device. Furthermore, the wirability of devices formed with Kroell's technique is limited due to the single level of interconnection using refractory metal, which he discloses. Still further, the P channel device formed by Kroell has a poor hole mobility and a high junction leakage characteristic because of its fabrication in polycrystalline silicon, as is implied by Kroell. Finally, there are fabrication difficulties which could lead to gate integrity problems.